This invention relates to an electrically erasable and reprogrammable memory cell which is implemented in CMOS polycrystalline silicon transistor technology and, more particularly, to an improved EPROM cell.
EPROM cells, which are similar in construction to field effect transistors, but additionally include a floating gate between the control gate and the control electrode of the transistor are already known. Essentially, an EPROM cell is programmed by applying certain voltages sufficient to draw electron charges through a thin insulator which become trapped in the conductive floating gate. After removing the applied voltage, the charge remains on the floating gate and leaks away only very slowly since the floating gate, which may be a thin film of polycrystalline silicon, is enveloped entirely by electrically insulating material. This condition increases the threshold voltage of the transistor, thereby rendering it cut off in response to normal read operation voltages. Hence, during reading of a transistor cell so programmed, the transistor will remain nonconductive and thus represent a high impedance between the source and drain terminals.
A known EPROM cell construction is shown in enlarged cross-section in FIGS. 1A and 1B, which respectively are sectional views taken along lines 1A--1A and 1B--1B of the FIG. 2 lay-out of the cell. In this structure, a first layer 1 of polycrystalline silicon (hereinafter sometimes called the "poly-I layer"), which serves as the floating gate, is spaced and insulated from a second polycrystalline silicon layer 2 ("poly-II layer"), which serves as the control gate, by an insulating oxide layer 4. The poly I layer is insulated from the semiconductor substrate S by a first gate oxide layer 3, and a source region 6 and a drain region 7 are formed in the substrate at opposite sides of the poly I layer (as viewed in FIG. 1B). The individual cells of the array shown in FIG. 2 are separated from each other by an oxide layer 5 deposited on the substrate.
The operation of this known EPROM cell is critically dependent on the thickness of the oxide layer 4 which separates the poly-I and poly-II layers in that it determines the coupling efficiency between the control gate and the floating gate of the cell; the thinner the insulating layer the greater the capacitance between the conductive layers. However, it is difficult to reproducibly form the interpoly layer so as to have a thickness which is optimum for coupling efficiency and which, at the same time, is of a quality to avoid current leakage from the floating gate which, of course, adversely affects the period of time that information can be stored. If the insulating layer is made thick enough to insure against current leakage, the capacitance between the control gate and floating gate is correspondingly smaller with the consequence that higher voltages, or longer programming times, are required to trap sufficient electrons in the floating gate.
From the foregoing, it can be seen that a need exists for an EPROM cell and memory array whose operation is less dependent than known devices on the thickness of the insulating layer separating the control gate and floating gate without compromising other features of the memory and is of a construction which will allow the insulating layer to be independently grown over the polycrystalline silicon film that serves as the floating gate.